Motivation
Virtually every presentation in electrical engineering begins with a slide of Moore's Law, which shows the exponential growth in the number of devices on a chip with time. Similar graphs also show the related shrinking of device dimensions with time. As the relevant device dimensions shrink to smaller and smaller levels, previous assumptions and simplifications of device physics are no longer valid, and standard device designs fail. Many research efforts are currently searching for new device and circuit designs to replace the current dominant silicon CMOS.
Recently, much attention has been focused on new kinds of devices, whose nanometer-scale sizes allow them to exploit classical Coulomb Blockade and quantum size effects. Quantum dots and single electron tunneling transistors (SETs) are examples of such devices. These devices have the potential for high device density, low power consumption, and increased functionality.
Coulomb Blockade and quantum size effects have been produced in devices larger than nanometer-scale, but only at extremely low temperatures. In order for these kinds of devices to have any hope of widespread application they must be operable at room temperature, which requires ultra-small, uniform dimensions. Current lithography processes cannot generally deliver the necessary resolutions, and standard etching methods often damage surfaces. New fabrication methods are of great interest.